Name: | verilator |
---|---|
Version: | 3.922 |
Release: | 1.el7 |
Architecture: | x86_64 |
Group: | Unspecified |
Size: | 9775950 |
License: | LGPLv3 or Artistic 2.0 |
RPM: | verilator-3.922-1.el7.x86_64.rpm |
Source RPM: | verilator-3.922-1.el7.src.rpm |
Build Date: | Wed May 02 2018 |
Build Host: | x86-ol6-builder-03.us.oracle.com |
Vendor: | Oracle America |
URL: | http://www.veripool.com/verilator.html |
Summary: | A fast simulator for synthesizable Verilog |
Description: | Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. |
- 3.922 bump, fixes rhbz #1557720
- Escape macros in %changelog
- 3.920 bump - Disabled tests until upstream fixes the issue - Added BR to fix EPEL7 build - Fixes rhbz #1250122 and rhbz #1494887
- 3.910 bump - License corrected to (LGPLv3 or Artistic 2.0)
- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Binutils_Mass_Rebuild
- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Mass_Rebuild
- Rebuilt for https://fedoraproject.org/wiki/Fedora_26_27_Mass_Rebuild
- Rebuilt for https://fedoraproject.org/wiki/Fedora_26_Mass_Rebuild
- Attempt to rebuilt on rawhide due dependency problems
- Rebuilt for new upstream version 3.890 - Spec clean up plus fixes rhbz #1087393 and rhbz #1358609