[ol8_u3_baseos_base] microcode_ctl-4:20200609-2.0.1.el8.x86_64

This package provides microcode update files for Intel x86 and x86_64 CPUs.

The microcode update is volatile and needs to be uploaded on each system
boot i.e. it isn't stored on a CPU permanently; reboot and it reverts
back to the old microcode.

Package name "microcode_ctl" is historical, as the binary with the same name
is no longer used for microcode upload and, as a result, no longer provided.

Changelog (Show File list) (Show related packages)

• Mon Aug 17 2020 Todd Vierling <todd.vierling@oracle.com> - 4:20200609.2.0.1

  - add support for UEK6 kernels
  - remove no longer appropriate caveats for 06-2d-07 and 06-55-04

• Mon Jun 22 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200609-2

  - Blacklist latest microcode revision for 06-[89]e-0x CPUs (AML-Y,
    CFL-H/S/U/Xeon E, CML-Y, KBL-G/H/S/X/U/Y/Xeon E3 v6, WHL-U) on Dell systems,
    use revision 0xae/0xb4/0xb8 by default, provide the latest revision
    and intermediate revision 0xca in caveats (#1807960, #1846097).

• Mon Jun 15 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200609-1

  - Update Intel CPU microcode to microcode-20200609 release (#1845967):
    - Fixed a typo in the release note file.

• Mon Jun 15 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200602-5

  - Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.

• Mon Jun 15 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200602-4

  - Enable 06-55-04 (SKL-X/W) caveat by default.

• Sun Jun 14 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200602-3

  - Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision
    0xdc, use 0xd6 by default (#1846119).

• Thu Jun 04 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200602-2

  - Avoid temporary file creation, used for here-documents in check_caveats
    (#1839163).

• Wed Jun 03 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200602-1

  - Update Intel CPU microcode to microcode-20200602 release, addresses
    CVE-2020-0543, CVE-2020-0548, CVE-2020-0549 (#1795354, #1795356, #1827184):
    - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;
    - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e
      up to 0x2f;
    - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25
      up to 0x26;
    - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;
    - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21
      up to 0x22;
    - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6
      up to 0xdc;
    - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151
      up to 0x1000157;
    - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode
      (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065
      up to 0x2006906;
    - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c
      up to 0x4002f01;
    - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c
      up to 0x5002f01;
    - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6
      up to 0xdc;
    - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca
      up to 0xd6;
    - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca
      up to 0xd6;
    - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca
      up to 0xd6;
    - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca
      up to 0xd6;
    - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode
      from revision 0xca up to 0xd6;
    - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision
      0xca up to 0xd6;
    - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca
      up to 0xd6;
    - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;
    - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca
      up to 0xd6;
    - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.

• Fri May 22 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200520-1

  - Update Intel CPU microcode to microcode-20200520 release (#1783103):
    - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f
      up to 0x621;
    - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718
      up to 0x71a.

• Tue May 12 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200508-1

  - Update Intel CPU microcode to microcode-20200508 release (#1783103):
    - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46
      up to 0x78.
  - Change the URL to point to the GitHub repository since the microcode download
    section at Intel Download Center does not exist anymore.