Name: | verilator |
---|---|
Version: | 5.022 |
Release: | 3.el9 |
Architecture: | x86_64 |
Group: | Unspecified |
Size: | 26177666 |
License: | LGPL-3.0-only OR Artistic-2.0 |
RPM: | verilator-5.022-3.el9.x86_64.rpm |
Source RPM: | verilator-5.022-3.el9.src.rpm |
Build Date: | Thu Apr 11 2024 |
Build Host: | build-ol9-x86_64.oracle.com |
Vendor: | Oracle America |
URL: | https://veripool.org/verilator/ |
Summary: | A fast simulator for synthesizable Verilog |
Description: | Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. |
- Do not package tests
- Improve conformance to modern Fedora packaging guidelines - Break out packages - Remove CC0 content
- Update to 5.022 - Fix SPDX License identifier - Add CMake for tests - Fix runtime dependency check - Fix runtime version checck - Fix multithreading bug that causes spurious failures - Default to using tcmalloc
- update verilator to 5.020 fixes rhbz#2239297
- Rebuilt for https://fedoraproject.org/wiki/Fedora_40_Mass_Rebuild
- fix build requires
- update to verilator-5.014
- Rebuilt for https://fedoraproject.org/wiki/Fedora_39_Mass_Rebuild
- Rebuilt for https://fedoraproject.org/wiki/Fedora_38_Mass_Rebuild
- Update to 4.226, enabled tests, spec cleanup and modernization - Fixes rhbz#1933296 rhbz#2047099 and rhbz#2026957