[ol10_u0_developer_EPEL] verilator-5.030-12.el10_0.x86_64

Name:	verilator
Version:	5.030
Release:	12.el10_0
Architecture:	x86_64
Group:	Unspecified
Size:	21463985
License:	LGPL-3.0-only OR Artistic-2.0
RPM:	verilator-5.030-12.el10_0.x86_64.rpm
Source RPM:	verilator-5.030-12.el10_0.src.rpm
Build Date:	Mon Dec 23 2024
Build Host:	build-ol10-x86_64.oracle.com
Vendor:	Oracle America
URL:	https://veripool.org/verilator/
Summary:	A fast simulator for synthesizable Verilog
Description:	Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.

Sat Dec 14 2024 Nolan Poe <npgo22@gmail.com> - 5.030-11
```
- Do not use z3 and gperftools in CentOS/RHEL builds
```

Sat Dec 14 2024 Nolan Poe <npgo22@gmail.com> - 5.030-10

- Do not build with tcmalloc and z3, which are unavailable in c10s

Sat Dec 14 2024 Nolan Poe <npgo22@gmail.com> - 5.030-9
```
- minor typo
```
Thu Dec 05 2024 Nolan Poe <npgo22@gmail.com> - 5.030-8
```
- Update tests
```
Thu Dec 05 2024 Nolan Poe <npgo22@gmail.com> - 5.030-7
```
- Disable some hardcoded paths in binary
```
Thu Dec 05 2024 Nolan Poe <npgo22@gmail.com> - 5.030-6
```
- Do not set build flags during testing
```
Wed Dec 04 2024 Nolan Poe <npgo22@gmail.com> - 5.030-5
```
- Packit support
```
Wed Dec 04 2024 Nolan Poe <npgo22@gmail.com> - 5.030-4
```
- Re-enable warnings
```
Wed Dec 04 2024 Nolan Poe <npgo22@gmail.com> - 5.030-3
```
- Add initial gating tests
```
Wed Dec 04 2024 Nolan Poe <npgo22@gmail.com> - 5.030-2
```
- Remove legacy changelog
```