[ol10_u0_developer_EPEL] verilator-5.030-12.el10_0.x86_64

Name:verilator
Version:5.030
Release:12.el10_0
Architecture:x86_64
Group:Unspecified
Size:21463985
License:LGPL-3.0-only OR Artistic-2.0
RPM: verilator-5.030-12.el10_0.x86_64.rpm
Source RPM: verilator-5.030-12.el10_0.src.rpm
Build Date:Mon Dec 23 2024
Build Host:build-ol10-x86_64.oracle.com
Vendor:Oracle America
URL:https://veripool.org/verilator/
Summary:A fast simulator for synthesizable Verilog
Description:
Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis
assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is
especially well suited to create executable models of CPUs for
embedded software design teams.

Filelist (Show Changelog) (Show related packages)